Ishwar Bhati

AI Research Engineer/Scientist
Intel Labs, Intel Corporation

Emails: ishwar.s.bhati [AT] intel [DOT] com; ishwar.bhati02 [AT] gmail [DOT] com
Website: https://ishwarbhati.github.io
LinkedIn: http://www.linkedin.com/in/ishwarbhati
Google Scholar: https://scholar.google.com/citations?user=DppJvVgAAAAJ&hl=en
Resume(CV)

Short Bio
Ph.D. in Computer Engineering with over 15 years of experience in hardware and software co-optimization, high-performance computing, and memory systems architecture. A prolific innovator with 10+ granted/filed US patents and a strong publication record in top-tier conferences (ISCA, VLDB, TMLR). Specialized expertise in optimizing AI/ML applications by leveraging advanced hardware features like AVX/SIMD and AMX on Intel® Xeon to develop innovative solutions for scalable vector search and deep learning architectures. Proven background in ASIC design and verification, including performance modeling and FPGA prototyping for complex memory controllers and processors (DDR2/3, SPARC). Proficient in C/C++, with a working knowledge of Python and Bash.

Education

University of Maryland, College Park (Sep 2010 - May 2014)
Ph.D. in Electrical and Computer Engineering
GPA: 4.0/4.0
Indian Institute Of Technology (IIT), Guwahati,India (June 2001 - May 2005)
B.Tech. in Electronics and Communication Engineering

Research

Optimizing Emerging AI/ML Applications
- Scalable Vector Search: optimizing approximate nearest neigbor (ANN) search on Intel hardware. Our work published in VLDB'23 and TMLR'24. Here is the link to our scalable vector search library
- Designing efficient compute and memory architecture for emerging applications like Deep Learning
Micro-architecture Research
- NVM based LLC: Proposed novel techniques to mitigate long NVM write latency (featured in ISCA-2018)
- Memory aware reordered source (MARS): to reshape the memory traffic for efficient memory bandwidth (US patent granted)
- Adaptive Width Aware Core (AWAC): we used simple heuristics to intelligently provision resources in the core dynamically (part of work featured in IEDM'2017)
Scalable DRAM Refresh
- Comprehensive evaluation and survey of DRAM refresh mechanisms, trade-offs and penalties. We clarify prevalent confusions with refresh options and timings available in JEDEC specified DDR devices (featured in Transaction on Computers, 2015)
- Proposed simple modification in DRAM device to enable refreshes reduction with optimized auto-refresh commands rather than in-efficient row-level refresh commands. (featured in ISCA-2014)
Energy Efficient Memory Systems
- Proposed novel techniques to simultaneously minimize two important types of DRAM energy components: background and refresh
- Our novel schemes called "Coordinated Refresh" schedule refresh operations and power down modes in an energy efficient fashion (featured in ISLPED-2013)
High Capacity Non-Volatile Memory (NVM)
- Contributed in the design of parametrized simulation infrastructure to study NVMs, with a focus on utilizing commodity NAND Flash as main memory candidate
- Explored emerging NVM technologies in order to find their appropriate position in the memory hierarchy using range of target applications (Featured in Intel Technology Journal - 2013)
Accurate Memory Simulations
- Designed set of techniques, when applied in a full-system simulator give reliable, accurate and less variable results
- Our techniques implemented on MARSSx86 integrated with DRAMSim2 for case study to show reduce variability in simulations

Work Experience

Research Scientist, Intel Corporation, (Dec 2015 - present)
- Scalable Vector Search: optimizing approximate nearest neigbor search on Intel hardware.
- Architecture research on emerging applications like Deep Learning
- Research on micro-architecture: NVM based LLC, Memory bandwidth efficiency and core resource partitioning algorithm
Senior Hardware Engineer, Oracle (formerly SUN Microsystem), Santa Clara (June 2014 - December 2015)
- Worked on performance modeling, projection and design space exploration of SPARC processor
- Responsible for modeling and maintaining memory-controller and database-accelerator modules
- Architectural explorations for future processors and debugging performance issues during bring-up
Research Assistant, Memory Systems Research Lab, Dept. of ECE, University of Maryland (Sep 2010 - May 2014)
- DRAM low power modes and refresh mechanisms
- Novel applications of persistent memory
- Reliable full-system simulation infrastructure
Graduate Intern, Intel Corporation, Hillsboro, USA ( June 2013 - August 2013)
- Quantified speed versus accuracy tradeoffs in memory modelling at several levels of abstraction (constant, analytical, queue-based, detailed etc.)
- Implemented and integrated a memory model, which is 10x faster than the cycle accurate DRAMSim2 and is within 10% of accuracy
- Technical Mentor: Emily Shriver, Strategic CAD Labs (SCL)
Senior ASIC Engineer, LSI Corporation, India (Jan 2009 - July 2010)
- RTL design and verification of DDR2/3 Memory Agent and DDR PHY
- Architecture of DDR3 training sequence and write leveling algorithm
- Implementation of SystemVerilog and VMM based automated testbench
ASIC Design and Verification Engineer, Nevis Networks Pvt. Ltd., India (July 2005 - June 2006, May 2007-Jan 2009)
- Verification of DRAM Control module in a 96-core Network Processor
- SystemC modeling and Full Chip Verification environment integration
- Prototyping of memory controller on Xilinx's Vertex-4 based FPGA board
Design Engineer, STMicroelectronics , India (June 2006 - May 2007)
- Modelling and design of Wireless USB Medium Access Control (MAC) Chip modules
Summer Intern, KNU, Daegu , South Korea (May 2004 - July 2004)
- Worked on speech enhancements and implemented Dynamic Time Warping (DTW) on TI-DSK 6711 using Simulink

Selected Publications

Mariano Tepper, Ishwar Singh Bhati, Cecilia Aguerrebere, Mark Hildebrand, Ted Willke, "LeanVec: Search your vectors faster by making them fit", Transactions on Machine Learning Research(TMLR), 2024. (selected as featured certification and presented as poster in ICLR 2025)
Mariano Tepper, Ishwar Singh Bhati, Cecilia Aguerrebere, Ted Willke, "GleanVec: Accelerating vector search with minimalist nonlinear dimensionality reduction", arXiv, 2024.
Cecilia Aguerrebere, Mark Hildebrand, Ishwar Singh Bhati, Theodore Willke, Mariano Tepper, "Locally-Adaptive Quantization for Streaming Vector Search", arXiv, 2024.
Cecilia Aguerrebere, Ishwar Bhati, Mark Hildebrand, Mariano Tepper, Ted Willke, "Similarity search in the blink of an eye with compressed indices", Proceedings of the VLDB Endowment, 2023.
Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, and Hong Wang, "MARS: Memory Aware Reordered Source", arXiv:1808.03518, August 2018.
Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian A. Young, and Hong Wang, "Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM based Last Level Cache", [Slides] " Proc. 45th International Symposium on Computer Architecture (ISCA 2018), Los Angeles, CA, June 2018.
Kaushik Vaidyanathan, Daniel H Morris, Uygar E Avci, Ishwar S. Bhati, Lavanya Subramanian, Jayesh Gaur, Huichu Liu, Sreenivas Subramoney, Tanay Karnik, Hong Wang, and Ian A Young, "Overcoming interconnect scaling challenges using novel process and design solutions to improve both high-speed and low-power computing modes", " Electron Devices Meeting (IEDM), 2017 IEEE International.
Ishwar Bhati, Mu-Tien Chang , Zeshan Chishti, Shih-Lien Lu, and Bruce Jacob, "DRAM Refresh Mechanisms, Penalties, and Trade-Offs", IEEE Transactions on Computers, vol. 65, no. 1, pp. 108-121. January 2016.
Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, and Bruce Jacob, "Flexible auto-refresh: Enabling scalable and energy efficient DRAM refresh reductions,", " Proc. 42nd International Symposium on Computer Architecture (ISCA 2015). . Portland, OR, June 2015.
Ishwar Bhati, Zeshan Chishti, and Bruce Jacob, "Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling", Proc. 2013 International Symposium on Low Power Electronics and Design (ISLPED 2013). Beijing China, September 2013.
Jim Stevens, Paul Tschirhart, Mu-Tien Chang, Ishwar Bhati, Peter Enns, James Greensky, Zeshan Chishti, Shih-Lien Lu, and Bruce Jacob, "An Integrated Simulation Infrastructure for the Entire Memory Hierarchy: Cache, DRAM, Nonvolatile Memory, and Disk,", Intel Technology Journal (ITJ), vol. 17, no. 1, 2013.

Ph.D. Thesis

Ishwar Bhati, "Scalable and Energy-Efficient DRAM Refresh Techniques", May, 2014.
Patents

Maria Cecilia Aguerrebere Otegui, Ishwar Bhati, Mark Hildebrand, Mariano Tepper, Theodore Willke, "Locally-adaptive vector quantization for similarity search", US Patent application filed, 2024

Mark Hildebrand, Mariano Tepper, Maria Cecilia Aguerrebere Otegui, Ishwar Singh Bhati, Theodore Willke, "TURBO LOCALLY-ADAPTIVE VECTOR QUANTIZATION FOR HIGH-PERFORMANCE DISTANCE COMPUTATIONS", US Patent application filed, 2024

Maria Cecilia Aguerrebere Otegui, Ishwar Singh Bhati, Mark Hildebrand, Mariano Tepper, Theodore Willke, "MULTI-MEANS LOCALLY-ADAPTIVE VECTOR QUANTIZATION FOR MEMORY EFFICIENT AND HIGH-PERFORMANCE STREAMING SIMILARITY SEARCH", US Patent application filed, 2024

Mariano Tepper, Ishwar Singh Bhati, Maria Cecilia Aguerrebere Otegui, Mark Hildebrand, Theodore Willke, "Dimensionality reduction technology to accelerate high-dimensional vector searches and index construction", US Patent application filed, 2024

Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das, Ashutosh Garg, Chandra S Gurram, Junjie Gu, Guei-Yuan Lueh, Subramaniam Maiyuran, Jorge E Parra, Sudarshan Srinivasan, Varghese George, "Instructions and logic for vector multiply add with zero skipping", US Patent granted, 2023

Ishwar S Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, "Memory aware reordered source", US Patent granted, 2020

Ishwar S Bhati, Huichu Liu, Jayesh Gaur, Kunal Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Hong Wang, Ian A Young, "Write congestion aware bypass for non-volatile memory, last level cache (LLC)", US Patent granted, 2019

Kunal Kishore Korgaonkar, Ishwar S Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Hong Wang, Ian A Young, "Method and apparatus for reducing write congestion in non-volatile memory based last level caches", US Patent granted, 2018

Ishwar Bhati, Zeshan Chishti and Shih-Lein L. Lu, "Techniques to Reduce Memory Cell Refreshes for a Memory Device", US patent granted, 2016

Ishwar Bhati and Zeshan Chishti, "Coordinating Power Mode Switching and Refresh Operations in a Memory Device", US Patent granted, 2015